FPGA Design Verification Engineer

Key Responsibilities

Support the FPGA verification team in ongoing and upcoming projects or new methodology initiatives.

Assist in the development and implementation of innovative verification and debugging solutions.

Document technical specifications clearly and maintain organized records of project progress.

Collaborate closely with verification team members to understand and improve workflows and methodologies.

Prepare and present updates and findings to stakeholders as required.

Qualifications

Skills and Qualifications:

Familiarity with HDL languages (VHDL, Verilog, SystemVerilog).

Experience or knowledge in scripting languages such as Tcl, Perl, or Python.

Prior experience or exposure to FPGA tools (Quartus or Vivado) would be advantageous.

Strong willingness to learn new skills and technologies.

Ability to work collaboratively within a team environment.

Good communication skills and ability to clearly present project details and outcomes.

Job Type

Regular

Shift

Shift 1 (India)

Primary Location:

Regus, Madhapur

Additional Locations:

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.